Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Many technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Research and development in the existing package technologies may embody a number of different directions.
One proven way to reduce cost is to use package technologies with existing manufacturing methods and equipments. Unfortunately, the reuse of existing manufacturing processes does not typically result in the reduction of package dimensions.
In response to the demands for improved packaging, many innovative package designs have been brought to market. The multi-chip module has achieved a prominent role in reducing the board space used by modern electronics. However, multi-chip modules, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. When die are mounted and connected to a substrate, the die and connections can be tested, and only known-good-die (“KGD”) free of defects are then assembled into larger circuits.
Other assembly and manufacturing defects may be encountered when the substrate has a package molding compound applied or when the individual devices are singulated from a larger strip containing multiple devices. In some cases, the package molding compound may become extruded onto the surface of the substrate beyond the intended profile. This may contaminate electrical contacts intended for further assembly or test. There may also be complications during the singulation process that can cause a delamination of the package molding compound from the die surface. The delamination can cause the electrical connections between the die and the substrate to break.
Several packaging techniques may stack multiple integrated circuit dice in a single package or form a package-in-package (PIP) stack or a combination thereof. Other approaches include package level stacking or package-on-package (POP). These techniques include stacking of two or more packages to form a single device. Assembly process yields are less of an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack. However, stacking integrated devices, package-in-package, package-on-package, or combinations thereof have assembly process difficulties caused by some packages having contamination on the electrical connections or broken electrical connections due to singulation stresses and delamination.
Thus, a need still remains for a base package system for integrated circuit package stacking providing low cost manufacturing, improved yields, reduction of integrated circuit package dimensions, and flexible integration configurations. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.